Revolutionizing EV Drivetrains: Large-Silicon-Carbide-Chip Power Modules Promise Higher Efficiency and Power Density
The relentless pursuit of longer range, faster charging, and more compact electric vehicles (EVs) is driving a quiet revolution deep within the powertrain. While consumers focus on battery capacity and aerodynamic design, engineers are waging a critical battle at the semiconductor level, where the efficiency of converting battery power into wheel torque is decided. A groundbreaking new study published in the Journal of Power Supply details a significant leap forward in this domain, proposing a high-power-density silicon carbide (SiC) power module design that leverages large-format SiC chips to overcome longstanding challenges in current and temperature distribution. This innovation, spearheaded by researchers from the Institute of Electrical Engineering at the Chinese Academy of Sciences, promises to be a pivotal step in the evolution of next-generation EV motor drives, potentially unlocking new levels of performance and reliability.
The heart of an EV’s electric drivetrain is the inverter, a sophisticated power electronics unit responsible for converting the direct current (DC) from the battery into the precise alternating current (AC) needed to drive the electric motor. For decades, this role was dominated by silicon-based Insulated Gate Bipolar Transistors (IGBTs). However, as the demands of the EV market have escalated, the inherent limitations of silicon—particularly its relatively high power losses and limited operating temperature—have become increasingly apparent. These losses, which manifest as heat, not only waste precious battery energy, reducing the vehicle’s overall range, but also necessitate complex, heavy, and expensive cooling systems.
Enter silicon carbide, a wide-bandgap semiconductor material that has emerged as a game-changer. SiC devices offer a compelling set of advantages over their silicon counterparts. They boast a much higher breakdown voltage, allowing them to operate at higher system voltages (such as the emerging 800V architectures), which in turn reduces current for the same power level and cuts resistive losses. They exhibit significantly lower switching and conduction losses, directly translating to higher system efficiency. Perhaps most crucially, SiC has a superior thermal conductivity, meaning it can handle more heat and operate reliably at higher junction temperatures. Collectively, these properties enable SiC-based inverters to be smaller, lighter, and more efficient, directly contributing to the core goals of the EV industry: extended range and reduced vehicle weight.
Despite these advantages, scaling SiC technology to the multi-hundred-ampere currents required for high-performance EVs presents a formidable engineering challenge. The most common approach has been to parallel numerous smaller SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) chips within a single power module. This strategy, employed in popular packaging formats like the Hybrid PACK Drive (HPD), allows manufacturers to achieve the necessary current rating by summing the capacity of many individual devices. For instance, a typical 680-ampere module might use 16 smaller chips, each rated for around 40-50 amperes, connected in parallel.
This parallel architecture, however, introduces a critical vulnerability: current and temperature imbalance. No two semiconductor chips are perfectly identical, even when produced on the same wafer. There are inherent variations in key parameters such as threshold voltage (Vth) and on-state resistance (Rds(on)). Studies have shown that these parameters can vary by as much as ±40% for Vth and ±15% for Rds(on) across a production batch. When these mismatched chips are connected in parallel, the chip with the lower Rds(on) will naturally conduct more current than its neighbors. This creates a vicious cycle: the higher current leads to greater power dissipation and a higher junction temperature in that specific chip. Although SiC MOSFETs have a positive temperature coefficient for Rds(on)—meaning resistance increases with temperature, which provides a natural, self-correcting mechanism for current sharing—this negative feedback loop is often too slow to fully compensate for the initial imbalance, especially under dynamic load conditions like rapid acceleration or regenerative braking. The result is a module where some chips are significantly hotter and more stressed than others, leading to “hotspots.”
These hotspots are more than just a thermal management nuisance. They are a primary driver of long-term reliability concerns. The accelerated aging of semiconductor materials and the degradation of packaging materials (like solder joints and dielectric substrates) are highly temperature-dependent processes. A chip operating at 180°C will degrade orders of magnitude faster than one operating at 150°C. Uneven temperature distribution thus creates a scenario where the entire module’s lifespan is dictated by the weakest, hottest chip, not the average. Furthermore, the stress from thermal cycling—repeated heating and cooling—can cause mechanical fatigue and eventual failure at the interfaces between different materials in the package. This risk is amplified when temperature gradients across the module are large. Therefore, achieving uniform current and temperature distribution is not merely an efficiency goal; it is a fundamental requirement for ensuring the long-term durability and safety of the power module, a critical component in a vehicle.
Recognizing the limitations of the “many small chips” approach, the research team led by Dongrun Li and Puqi Ning has proposed a paradigm shift: instead of paralleling many small chips, they advocate for using fewer, much larger SiC chips. Their work is built upon the development of a new generation of large-format SiC MOSFETs. The study specifically utilizes a 1200V, 3.5mΩ chip developed by SiChain Semiconductors in Ningbo. This single large chip has a much higher intrinsic current-carrying capacity—up to 350 amperes at 150°C—compared to the smaller 16mΩ chips typically used in HPD modules.
The core hypothesis of the research is elegantly simple: by reducing the number of paralleled devices, the impact of parameter mismatch is dramatically diminished. If a module can achieve its target current with four large chips instead of sixteen smaller ones, there are simply fewer opportunities for significant imbalance to occur. Even if the relative variation in Rds(on) is the same, the absolute difference in current between the highest- and lowest-conducting chips is expected to be smaller, leading to a more uniform temperature profile across the module.
To validate this concept, the team designed and fabricated a prototype high-power-density SiC power module using this large-chip strategy. A critical enabler of this design is the adoption of a multilayer Direct Bonded Copper (DBC) substrate packaging technology. Unlike traditional wire-bonded packages, where long, thin wires connect the chip to the terminals and introduce significant parasitic inductance, the multilayer DBC approach creates a vertical, sandwich-like structure. The large SiC chips are placed between two DBC layers, and the connections are made through direct metallization and soldering. This design drastically reduces the parasitic inductance in the main power loop, which is crucial for high-speed switching and minimizing voltage overshoots that can damage the device. More importantly for this study, the symmetric, planar layout of the multilayer DBC provides inherently balanced current paths and thermal conduction paths for the paralleled chips. This physical symmetry complements the large-chip strategy by ensuring that any minor electrical or thermal differences are not exacerbated by an asymmetric package design.
The researchers conducted a rigorous double-pulse test on their prototype module, a standard method for evaluating the dynamic switching characteristics of power semiconductors. The results were compelling. The module successfully operated at an 800V DC bus voltage with a peak current of 350 amperes at a junction temperature of 150°C, demonstrating its robust electrical performance. In a direct comparison, a conventional wire-bonded module using the same type of large chip began to exhibit severe gate signal oscillations at a much lower voltage of 650V, highlighting the superior electromagnetic performance and stability of the multilayer DBC package. This successful experimental validation proved that the large-chip, low-inductance packaging concept is not just theoretical but is a viable and high-performing solution.
While the experimental results confirmed the module’s basic functionality, the true power of the research lies in its sophisticated simulation analysis, which delves into the complex interplay between electrical and thermal behavior. The team constructed a coupled electro-thermal simulation model, a powerful tool that links an electrical circuit model of the paralleled MOSFETs with a detailed thermal network model of the module’s physical structure. This thermal model, based on the Foster network approach, accurately represents how heat flows from the chip’s active area (the junction) through the various layers of the package (solder, DBC, baseplate) to the heatsink.
The simulation was designed to mimic a realistic operating scenario: a linearly increasing load, simulating an EV’s acceleration. The researchers ran two sets of simulations. The first set ignored the temperature feedback effect, essentially assuming the chips’ electrical parameters remained constant regardless of temperature. In this scenario, the current imbalance grew steadily as the load increased, and the simulation predicted a significant maximum temperature difference between the hottest and coolest chip in the module.
The second, and more realistic, set of simulations incorporated the temperature feedback. As the temperature of each virtual chip rose due to its power dissipation, the model dynamically adjusted its Rds(on) according to the known positive temperature coefficient of SiC. This created a closed-loop system where temperature influenced current, and current influenced temperature.
The results of this coupled simulation were the study’s most significant finding. As expected, when temperature feedback was included, the maximum temperature difference between the chips was smaller than in the no-feedback case, confirming the self-balancing effect of the positive temperature coefficient. However, the key insight was the comparison between two different module designs: one using four of the large 3.5mΩ chips, and another using sixteen of the smaller 16mΩ chips, both designed to handle the same total current.
The simulation clearly showed that the module with four large chips maintained a smaller maximum temperature difference than the module with sixteen small chips, even when the temperature feedback was active. This numerical evidence strongly supports the central thesis: using fewer, larger chips is a more effective strategy for achieving uniform temperature distribution than relying solely on the material’s inherent self-balancing properties in a high-count parallel configuration. The reduction in the number of paralleled devices directly translates to better thermal management and, by extension, higher reliability.
This research represents a significant contribution to the field of power electronics for electric vehicles. It moves beyond simply adopting SiC technology and addresses a fundamental system-level challenge in its implementation. By combining a novel device strategy (large chips) with an advanced packaging technology (multilayer DBC), the team has demonstrated a clear path to higher power density and improved reliability. The implications are far-reaching. For EV manufacturers, this technology could enable the development of more compact and lighter inverters, freeing up space and reducing overall vehicle weight, which further improves efficiency and range. The enhanced thermal uniformity also means the inverter can be pushed to higher power levels with greater confidence in its long-term durability, supporting the trend towards higher-performance electric vehicles.
Furthermore, this work highlights the importance of a holistic design approach. The success is not due to a single breakthrough but to the synergistic integration of advancements in semiconductor device fabrication, power module packaging, and system-level simulation. It underscores that the future of EVs will be built on such integrated innovations, where materials science, electrical engineering, and thermal management converge to solve complex real-world problems.
In conclusion, the study by Li, Ning, and their colleagues presents a compelling vision for the next generation of EV power electronics. By championing the use of large SiC chips within a low-inductance, symmetric package, they have devised a solution that directly tackles the critical issues of current and temperature imbalance. This approach not only promises higher efficiency and power density but also lays a stronger foundation for the long-term reliability that is essential for mass-market electric vehicles. As the automotive industry continues its electrified transformation, innovations like this will be the unsung heroes, working silently within the powertrain to make electric driving more efficient, more powerful, and ultimately, more sustainable.
Dongrun Li, Puqi Ning, Yuhui Kang, Tao Fan, Guangyin Lei, Wenhua Shi, Institute of Electrical Engineering, Chinese Academy of Sciences, Journal of Power Supply, DOI: 10.13234/j.issn.2095-2805.2024.3.93